FIG. 17 shows an example of connections between power semiconductor switching elements and a conventional semiconductor device (HVIC, High-Voltage Integrated Circuit) in an inverter or other power conversion device. Specifically, FIG. 17 shows an example of a half bridge, in which two power semiconductor switching elements (e.g., IGBTs) 114, 115 are connected in series. By alternately turning ON the upper-arm IGBT 115 and the lower-arm IGBT 114, the high potential or low potential are output alternately from the Vs terminal, which serves as the output terminal to supply an AC power to the L load 118. That is, the IGBT 114 and IGBT 115 are configured to operate so that when the high potential is output, the upper-arm IGBT 115 is turned ON while the lower-arm IGBT 114 is turned OFF, and when the low potential is output, the upper-arm IGBT 115 is turned OFF while the lower-arm IGBT 114 is turned ON. The diodes 116 and 117, which are reversely connected in parallel with the IGBTs 114, 115, are FWDs (Free Wheel Diodes). The driving semiconductor device 111 (HVIC) outputs a signal with GND as a reference as the gate signal for the lower-arm IGBT 114, and outputs a signal with the Vs terminal as a reference as the gate signal for the upper-arm IGBT 115. Hence, the driving semiconductor device 111 (HVIC) must be provided with a level shift function.
Among the symbols/references in the figures, Vss indicates a high-potential side of a high-voltage power supply, GND is the ground, Vs is an intermediate potential, H-VDD is a high-potential side of a low-voltage power supply with a Vs terminal as a reference, L-VDD is a low-potential side of the low-voltage power supply with the GND as a reference, H-IN is an input terminal from which an input signal is input to the gate of a low-side C-MOS circuit (low-potential side low-voltage circuit region) connected to the level-up circuit, L-IN is an input terminal from which an input signal is input to the gate of the low-side C-MOS circuit (low-potential side low voltage circuit region) connected to the gate of the lower-arm IGBT 114, H-OUT is an output terminal from which an output signal of the high-side C-MOS circuit (high-potential side low-voltage region) is output to the gate of the upper-arm IGBT 115, L-OUT is an output terminal from which an output signal is output to the gate of the lower-arm IGBT 114, ALM-IN is an input terminal to which an input signal of a detection signal is input when detecting temperature and overcurrent of the upper-arm IGBT 115, and ALM-OUT is an output terminal from which an output signal of the detection signal is output with a lowered level (level-down-converted detection signal). Moreover, n and p indicate conduction types, where n is an n-type and p is a p-type.
Referring to FIGS. 18 and 19, which are circuit diagrams showing the level shift circuits and the peripheral circuits, the driving semiconductor device 111 includes a level-up circuit (a circuit diagram illustrated in FIG. 18) and a level-down circuit (a circuit diagram illustrated in FIG. 19). As peripheral circuits, a low-side C-MOS circuit transmits the input signal from the level shift circuit, and a high-side C-MOS circuit transmits the output signal from the level shift circuit to the upper-arm IGBT 115.
In FIG. 18, when the input signal (H-IN) is input to the low-side circuit, the signal passes through its C-MOS circuit and is input to the gate of the n-channel MOSFET 41 of the level-up circuit. This signal turns the n-channel MOSFET 41 ON and OFF. The output signal from the level-up circuit is output from its output portion 101, to the C-MOS circuit of the high-side circuit, which outputs an ON/OFF output signal (H-OUT). This output signal is converted into a signal with Vs as a reference. This output signal is input to the gate of the upper-arm IGBT 115, to turn the upper-arm IGBT 115 ON and OFF. The level-up circuit of FIG. 18 is necessary when the upper-arm IGBT 115 is an n-channel device.
In FIG. 19, the level-down circuit employs a p-channel MOSFET 43, a level shift resistor 72, and a diode 76 connected in parallel with the level shift resistor 72. The ALM-IN signal is input to the gate of the C-MOS circuit of the high-side circuit, and the C-MOS circuit output signal is input to the gate of the p-channel MOSFET 43 of the level-down circuit. By turning ON and OFF the p-channel MOSFET 43, a low-side signal is output from the output portion 102 of the level-down circuit, and the signal with level lowered, which is output from the C-MOS circuit of the low-side circuit, is output from ALM-OUT to the low side as the detection signal.
FIGS. 20A and 20B show in detail the level shift circuit of a conventional semiconductor device (HVIC). FIG. 20A illustrates the level-up circuit diagram, and FIG. 20B illustrates the level-down circuit diagram. The level-up circuit shown in FIG. 20A comprises a level shift resistor 71, and an n-channel MOSFET 41, with its drain connected to the level shift resistor 71. The connection of the level shift resistor 71 and the n-channel MOSFET 41 serves as the output portion 101 of the level-up circuit. To prevent failure of the level shift resistor 71 when H-VDD is at a greatly lower potential than the GND potential (when an excessive negative voltage is applied), a diode 75 is connected in parallel with the level shift resistor 71. When an overvoltage is applied to H-VDD, the diode 75 advantageously prevents an excessive voltage from being applied to the gate of the MOSFET of the C-MOS circuit of the high-side circuit. Normally, a Zener diode is used as this diode. Also, the n-channel MOSFET 41 incorporates a body diode 42 (shown in phantom) reversely connected in parallel.
The level-down circuit shown in FIG. 20B comprises a p-channel MOSFET 43, with its drain connected to the level shift resistor 72. The connection portion between the level shift resistor 72 and p-channel MOSFET 43 serves as the output portion 102 of the level-down circuit. To prevent failure of the level shift resistor 72 when H-VDD is at a greatly lower potential than the GND potential (when an excessive negative voltage is applied), a diode 76 is connected in parallel with the level shift resistor 72. When an overvoltage is applied to H-VDD during the turn-ON operation of the MOSFET 43, the diode 76 advantageously prevents an overvoltage from being applied to the gate of the MOSFET of the C-MOS circuit of the low-side circuit. Also, the n-channel MOSFET 43 incorporates a body diode 44 (shown in phantom) reversely connected in parallel.
FIGS. 21 and 22 show the configuration of semiconductor devices employing a level-up circuit. FIG. 21 is a cross-sectional view of principal portions of a junction isolation-type semiconductor device, and FIG. 22 is a cross-sectional view of principal portions of an insulation-isolated type semiconductor device. In FIG. 21, an n-well region 2 and an n-well region 3 are formed at the surface of the p-type semiconductor substrate 1, which is connected to the GND potential. A C-MOS circuit of the low-side circuit is formed within the n-well region 2, while the level shift circuit and the C-MOS circuit of the high-side circuit are formed within the n-well region 3. The level shift n-channel MOSFET 41 is formed by forming a p-type region 51 within the n-well region 3, forming an n source region 53 and a p contact region 54 in the surface layer, forming an n drain region 52 in the surface layer of the n-well region 3, and forming a gate electrode 55, within a gate oxidation film intervening, on the p region 51 extending between the n source region 53 and the n drain region 52.
The drain region 52 of this n-channel MOSFET 41 is connected to the H-VDD via the level shift resistor 71 using surface metal wiring, and the connection portion between the drain region 52 and the level shift resistor 71 becomes the level-up circuit output portion 102. The output portion 102 outputs a low potential when this level-up n-channel MOSFET 41 is turned ON, and outputs a high potential when turned OFF, so that level shift operation, which is the signal transmission between different reference potentials, can be performed.
FIG. 22 shows a cross-sectional view of principal portions of a semiconductor device (HVIC) when an SOI substrate is used. The construction in FIG. 22 is different from that of FIG. 21 in that the GND reference n-well region 2 and Vs reference n-well region 3 correspond to an n-well region 6 and an n-well region 7, surrounded by insulating films 8, 9 on the surface of an n substrate 5. By this means, parasitic operation can be suppressed, and safer operation becomes possible.
Japanese Patent No. 3346763, corresponding to U.S. Pat. No. 6,597,550, discloses a high-voltage integrated circuit chip, and more specifically a circuit used to protect a high-voltage integrated circuit that drives power transistors in a half-bridge configuration, and which is a high-voltage integrated circuit chip having a resistor, between the substrate and the ground, to limit the current during negative-voltage spikes, for use with circuits whose excessive negative spikes at the output node are anticipated.
Further, Japanese Patent Laid-open No. 2001-25235 discloses a driving device in which, by inserting a diode between the drain electrode of a switching element belonging to a level shifter and the gate electrode of a MOS transistor belonging to an amplifier (C-MOS circuit), the reverse-bias effect is diminished. Further, Japanese Patent Publication No. 7-95680 discloses a level-up circuit driving the upper-arm p-channel MOSFET of a main circuit, in which a resistor is connected between the level shift resistor and the drain of an n-channel MOSFET.
For the connections shown in FIG. 17, Vss is approximately 1200 V, and when H-VDD is at a potential approximately 20 V higher than Vs the upper-arm IGBT 115 operates and the lower-arm IGBT 114 is turned OFF, in which case current flows from the upper-arm IGBT 115 to the L load 118. When from this state the IGBT 115 is turned OFF and the L load 118 attempts to maintain current, current flows from GND via the lower-arm FWD 116 and the Vs terminal drops to approximately −100 V below GND. When the potential at the terminal Vs is approximately −100 V, the potential at terminal H-VDD is approximately −80 V.
In the construction of FIG. 21, the p substrate 1 is at the GND potential. When the potential at the terminal Vs falls until the n-well region 3 is lower than the GND potential, the parasitic diode 45 formed by the p region 1 and n-well region 3 is forward-biased, and a large current flows. This current flows between the gate and source of the IGBT 115, and there is no resistance component limiting the current flow in this path, so that an extremely large pulse current flows. As a result of this pulse current, the semiconductor device (HVIC) can fail or malfunction.
Further, when a dielectric isolation technique is applied as in FIG. 22, the parasitic diode 45 formed from the p substrate 1 and n-well region 3 in FIG. 21 does not exist, but a large current flows via the body diode 42 of the MOSFET formed from the p region 51 of the level shift MOSFET 41 and n-region 7, resulting in the semiconductor device (HVIC) failing or malfunctioning.
Further, while Japanese Patent No. 3346763 (corresponding U.S. Pat. No. 6,597,550) discloses connecting a current-limiting resistor to the ground, this reference fails to mention any alternate connection location other than this location. Further, in Japanese Patent Laid-open No. 2001-25235, a diode is connected to diminish the reverse-bias effect, but there is no mention of connecting any current-limiting resistance. Further, in Japanese Patent Publication No. 7-95680, the resistor connected between the level shift resistor and the drain of the n-channel MOSFET acts to adjust the gate voltage input to the gate of the p-channel MOSFET on the high side, through voltage division with the level shift resistor. For example, in a 1200 V-class HVIC, to reduce power consumption, a level shift resistor of several tens of kΩ is used, and in this case the voltage-division resistor is also several tens of kΩ. Hence, the rise time and fall time of the gate input signal are made longer. That is, the value of the voltage-division resistance is chosen not as a value to limit current so that the body diode of the n-channel MOSFET does not fail when an excessive negative voltage is input to the high-voltage power supply terminal, but rather to obtain the desired gate voltage.
Accordingly, there remains a need for a level shift circuit and a semiconductor device (HVIC) that do not fail or malfunction even when a negative voltage is applied to the H-VDD terminal or Vs terminal, or when an ESD (Electro Static Discharge) surge is applied. The present invention addresses this need.